As integrated circuit devices become more highly integrated, the characteristics of these devices, for example, transistors, may continue to degrade. For example, a transistor may experience short channel effects, such as punch-through, Drain Induced Barrier Lowering (DIBL), sub-threshold swing, increased leakage current and the like.
To address the problems discussed above, integrated circuit manufacturers have provided double-gate-field-effect transistors and Fin-field effect transistors (Fin-FETs). Fin-FETs have gate electrodes on both sides of a channel, thus, allowing the gate electrodes to control channels on both sides. Accordingly, the likelihood of the occurrence of the short channel effect may be reduced.
Typically, methods of manufacturing Fin-FETs may include etching an integrated circuit substrate to form a fin, for example, a silicon fin, that defines a trench on the integrated circuit substrate. An insulation material may be provided in the trench or device isolation region to electrically separate neighboring fins. A surface of the insulation material may be recessed beneath a surface of the fins. In other words, after filling the trench with the isolation material, the isolation material is recessed beneath a top surface of the fin to expose sidewalls the fin. The isolation material may be recessed using a wet etchant.
However, the isolation material in the trench may be attacked during a subsequent cleaning process, which may result in the fins having various heights and a gate oxide layer having various thicknesses. Furthermore, the wet etchant may penetrate between the fin and the isolation material layer, thereby possibly generating a void in the isolation material layer. Accordingly, a subsequently formed gate-electrode material layer may penetrate into the void, causing an unwanted electrical connection between neighboring gate electrodes.